Learn how to incorporate your Vivado HLS design as an IP block into System Generator for DSP. See how a Vivado HLS design can be saved as an IP block and learn how this IP can be easily incorporated into a design in System Generator for DSP. For More Vivado Tutorials please visit: www.xilinx.com/training/vivado
Introduction to FPGA Design with Vivado HLS
http://www.xilinx.com/support/documentation/sw_manuals/ug998-vivado-intro-fpga-design-hls.pdf
Vivado HLS Tutorial
http://www.xilinx.com/support/document
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